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NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM Features
CAS Latency and Frequency
CAS Latency 2 2.5 Maximum Operating Frequency (MHz)* DDR333 (-6) DDR300 (-66) 133 133 166 150
* Double data rate architecture: two data transfers per clock cycle * Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver * DQS is edge-aligned with data for reads and is centeraligned with data for writes * Differential clock inputs (CK and CK) * Four internal banks for concurrent operation
* Data mask (DM) for write data * DLL aligns DQ and DQS transitions with CK transitions. * Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS * Burst lengths: 2, 4, or 8 * CAS Latency: 2, 2.5 * Auto Precharge option for each burst access * Auto Refresh and Self Refresh Modes * 7.8s Maximum Average Periodic Refresh Interval * 2.5V (SSTL_2 compatible) I/O * VDDQ = 2.5V 0.2V * VDD = 2.5V 0.2V * Package : 66pin TSOP-II / 60 balls 0.8mmx1.0mm pitch CSP.
Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edgealigned with data for Reads and center-aligned with data for Writes. The 256Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going high and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
Preliminary
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NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Pin Configuration - 400mil TSOP II
VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NU NC WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NU NC WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM* CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM* CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
66-pin Plastic TSOP-II 400mil
32Mb x 8 NT5DS32M8AT
64Mb x 4
NT5DS64M4AT
Column Address Table Organization 64Mb x 4 32Mb x 8 Column Address A0-A9, A11 A0-A9
*DM is internally loaded to match DQ and DQS identically.
Preliminary
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package
See the balls through the package.
64 X 4 1 VSSQ NC NC NC NC VREF 2 NC VDDQ VSSQ VDDQ VSSQ VSS CLK A12 A11 A8 A6 A4 3 VSS DQ3 NC DQ2 DQS DQM CLK CKE A9 A7 A5 VSS A B C D E F G H J K L M 7 VDD DQ0 NC DQ1 QFC NC WE RAS BA1 A0 A2 VDD 8 NC VSSQ VDDQ VSSQ VDDQ VDD CAS CS BA0 A10/AP A1 A3 9 VDDQ NC NC NC NC NC
32 X 8 1 VSSQ NC NC NC NC VREF 2 DQ7 VDDQ VSSQ VDDQ VSSQ VSS CLK A12 A11 A8 A6 A4 3 VSS DQ6 DQ5 DQ4 DQS DQM CLK CKE A9 A7 A5 VSS A B C D E F G H J K L M 7 VDD DQ1 DQ2 DQ3 QFC NC WE RAS BA1 A0 A2 VDD 8 DQ0 VSSQ VDDQ VSSQ VDDQ VDD CAS CS BA0 A10/AP A1 A3 9 VDDQ NC NC NC NC NC
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NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Input/Output Functional Description
Symbol CK, CK Type Input Function Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control of stacked devices. Chip Select: All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. The standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in addition to CS0, to allow upper or lower deck selection on stacked devices. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. During a Read, DM can be driven high, low, or floated. Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provide the row address for Active commands, and the column address and Auto Precharge bit for Read/Write commands, to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode Register Set command. Data Input/Output: Data bus. Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. No Connect: No internal electrical connection is present. Electrical connection is present. Should not be connected at second level of assembly. Supply Supply Supply Supply Supply DQ Power Supply: 2.5V 0.2V. DQ Ground Power Supply: 2.5V 0.2V. Ground SSTL_2 reference voltage: (VDDQ / 2) 1%.
CKE, CKE0, CKE1
Input
CS, CS0, CS1
Input
RAS, CAS, WE
Input
DM
Input
BA0, BA1
Input
A0 - A12
Input
DQ DQS NC NU VDDQ VSSQ VDD VSS VREF
Input/Output Input/Output
Preliminary
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM Ordering Information
Part Number NT5DS64M4AT-6 NT5DS32M8AT-6 NT5DS64M4AT-66 NT5DS32M8AT-66 NT5DS64M4AW-6 NT5DS32M8AW-6 NT5DS64M4AW-66 NT5DS32M8AW-66 Org. x4 2.5 x8 66 pin TSOP-II x4 2.5 x8 x4 2.5 x8 60 balls CSP x4 2.5 x8 150 2 133 DDR300 166 2 133 DDR333 150 2 133 DDR300 166 2 133 DDR333 CAS Latency Clock (MHz) CAS Latency Clock (MHz) Speed Package
Preliminary
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Block Diagram (64Mb x 4)
Control Logic
CKE CK CK CS WE CAS RAS
Command Decode
Bank1 Row-Address MUX Bank0 Row-Address Latch & Decoder
Bank2
Bank3 CK, CK DLL
Mode Registers
13
8192
Read Latch
Refresh Counter 13
4 4 MUX 4 DQS Generator 1
Sense Amplifiers Bank Control Logic
8192
8
Drivers
15
13
Bank0 Memory Array (8192 x 1024 x 8)
Data
Address Register
A0-A12, BA0, BA1
2
15
I/O Gating DM Mask Logic 1024 (x8) Column Decoder 10
COL0 8 8 Write FIFO & Drivers
Input Register 1 Mask 1 2 1 4 1 4 4
DQS 1 4 Receivers
DQ0-DQ3, DM DQS
2
8 4 clk clk out in Data CK, CK COL0
11
Column-Address Counter/Latch 1
COL0
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
Preliminary
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Block Diagram (32Mb x 8)
Control Logic
CKE CK CK CS WE CAS RAS
Command Decode
Bank1 Row-Address MUX Bank0 Row-Address Latch & Decoder
Bank2
Bank3 CK, CK DLL
Mode Registers
13
8192
Read Latch
Refresh Counter 13
8 8 MUX 8 DQS Generator 1
Sense Amplifiers Bank Control Logic
8192
16
Drivers
15
13
Bank0 Memory Array (8192 x 512 x 16)
Data
Address Register
COL0 I/O Gating DM Mask Logic
512 (x16)
2
16
2 16
8
8 8
Column Decoder 9 10 Column-Address Counter/Latch 1 COL0
8 clk clk out in Data CK, CK COL0
8
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
Preliminary
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Receivers
A0-A12, BA0, BA1
2
16 Write FIFO & Drivers
15
Input Register 1 Mask 1 1 1
DQS 1
DQ0-DQ7, DM DQS
NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Mode Register Operation
BA1 0* BA0 0* A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 BT A2 A1 A0 Address Bus Mode Register
Operating Mode
CAS Latency
Burst Length
A12 - A9 0 0 0
A8 0 1 0
A7 0 0 1
A6 - A0 Valid Valid VS**
Operating Mode Normal operation Do not reset DLL Normal operation in DLL Reset Vendor-Specific Test Mode Reserved A3 0 1 Burst Type Sequential Interleave
-
-
-
CAS Latency
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved Reserved 2 Reserved Reserved Reserved 2.5 Reserved A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1
Burst Length
A0 0 1 0 1 0 1 0 1 Burst Length Reserved 2 4 8 Reserved Reserved Reserved Reserved
VS** Vendor Specific * BA0 and BA1 must be 0, 0 to select the Mode Register (vs. the Extended Mode Register).
Preliminary
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Burst Definition
Starting Column Address Burst Length A2 2 0 0 4 1 1 0 0 0 0 8 1 1 1 1 0 0 1 1 0 0 1 1 A1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Type = Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Order of Accesses Within a Burst
Notes: 1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block. 3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definition on page 9. Read Latency The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Preliminary
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NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Extended Mode Register Definition
BA1 0* BA0 1* A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 0** A1 DS A0 DLL Address Bus Extended Mode Register
Operating Mode
Drive Strength
A12 - A3 0 A2 - A0 Valid Operating Mode Normal Operation All other states Reserved 0 1 Normal Reserved A1 Drive Strength
-
-
A2 0
QFC Disable A0 0 DLL Enable Disable
* BA0 and BA1 must be 1, 0 to select the Extended Mode Register (vs. the base Mode Register)
1
Preliminary
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NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM Commands
Truth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM devices. A verbal description of each commands follows.
Truth Table 1a: Commands
Name (Function) Deselect (Nop) No Operation (Nop) Active (Select Bank And Activate Row) Read (Select Bank And Column, And Start Read Burst) Write (Select Bank And Column, And Start Write Burst) Burst Terminate Precharge (Deactivate Row In Bank Or Banks) Auto Refresh Or Self Refresh (Enter Self Refresh Mode) Mode Register Set CS H L L L L L L L L RAS X H L H H H L L L CAS X H H L L H H L L WE X H H H L L L H L Address X X Bank/Row Bank/Col Bank/Col X Code X Op-Code MNE NOP NOP ACT Read Write BST PRE AR / SR MRS Notes 1, 9 1, 9 1, 3 1, 4 1, 4 1, 8 1, 5 1, 6, 7 1, 2
1. CKE is high for all commands shown except Self Refresh. 2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode Register.) 3. BA0-BA1 provide bank address and A0-A12 provide row address. 4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto Precharge feature (nonpersistent), A10 low disables the Auto Precharge feature. 5. A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are "Don' Care." t 6. This command is auto refreshif CKE is high; Self Refresh if CKE is low. 7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are "Don' Care" except for CKE. t 8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto Precharge enabled or for write bursts 9. Deselect and NOP are functionally interchangeable.
Truth Table 1b: DM Operation
Name (Function) Write Enable Write Inhibit 1. Used to mask write data; provided coincident with the corresponding data. DM L H DQs Valid X Notes 1 1
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NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Truth Table 2: Clock Enable (CKE)
1. 2. 3. 4. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge. Current state is the state of the DDR SDRAM immediately prior to clock edge n. Command n is the command registered at clock edge n, and action n is a result of command n. All states and sequences not shown are illegal or reserved.
CKE n-1 Current State Previous Cycle L L L L H H H H CKEn Current Cycle L H L H L L L H Command n Action n Notes
Self Refresh Self Refresh Power Down Power Down All Banks Idle All Banks Idle Bank(s) Active
X Deselect or NOP X Deselect or NOP Deselect or NOP Auto Refresh Deselect or NOP See "Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)" on page 13
Maintain Self-Refresh Exit Self-Refresh Maintain Power-Down Exit Power-Down Precharge Power-Down Entry Self Refresh Entry Active Power-Down Entry 1
1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t XSNR) period. A minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Preliminary
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NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)
Current State Any L L Idle L L L Row Active L L Read (Auto Precharge Disabled) L L L L L L H L L L H H L H L H H H L H H L L L L H L H H L L H H H H L H L L H L L H L L No Operation Active Auto Refresh Mode Register Set Read Write Precharge Read Precharge Burst Terminate Read Write Precharge Select column and start Read burst Select column and start Write burst Deactivate row in bank(s) Select column and start new Read burst Truncate Read burst, start Precharge Burst Terminate Select column and start Read burst Select column and start Write burst Truncate Write burst, start Precharge NOP. Continue previous operation Select and activate row 1-6 1-6 1-7 1-7 1-6, 10 1-6, 10 1-6, 8 1-6, 10 1-6, 8 1-6, 9 1-6, 10, 11 1-6, 10 1-6, 8, 11 CS H RAS X CAS X WE X Command Deselect Action NOP. Continue previous operation Notes 1-6
Write (Auto Precharge Disabled)
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t XSNR / tXSRD has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle state. Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the "row active" state. Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when t RP has been met. Once tRP is met, the bank is in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4. 5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once t RFC is met, the DDR SDRAM is in the "all banks idle" state. Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once t MRD is met, the DDR SDRAM is in the "all banks idle" state. Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank. 10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 11. Requires appropriate DM masking.
Preliminary
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NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
(Part 1 of 2)
Current State Any L Idle X L Row Activating, Active, or Precharging L L L Read (Auto Precharge Disabled) L L L L Write (Auto Precharge Disabled) L L L H X L H H L L H L L H H L H X H L L H H L H H L L H H X H H L L H H L H H L L No Operation Any Command Otherwise Allowed to Bank m Active Read Write Precharge Active Read Precharge Active Read Write Precharge Select and activate row Select column and start Read burst Select column and start new Write burst Select and activate row Select column and start new Read burst Select and activate row Select column and start Read burst Select column and start Write burst NOP/continue previous operation 1-6 1-6 1-6 1-7 1-7 1-6 1-6 1-7 1-6 1-6 1-8 1-7 1-6 CS H RAS X CAS X WE X Command Deselect Action NOP/continue previous operation Notes 1-6
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t XSNR / tXSRD has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See note 10. Write with Auto Precharge Enabled: See note 10. 4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle. 5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8. Requires appropriate DM masking. 9. A Write command may be applied after the completion of data output. 10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or t RP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).
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256Mb DDR333/300 SDRAM Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
(Part 2 of 2)
Current State CS L Read (With Auto Precharge) L L L L Write (With Auto Precharge) L L L RAS L H H L L H H L CAS H L L H H L L H WE H H L L H H L L Command Active Read Write Precharge Active Read Write Precharge Select and activate row Select column and start Read burst Select column and start new Write burst Action Select and activate row Select column and start new Read burst Select column and start Write burst Notes 1-6 1-7,10 1-7,9,10 1-6 1-6 1-7,10 1-7,10 1-6
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t XSNR / tXSRD has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See note 10. Write with Auto Precharge Enabled: See note 10. 4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle. 5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8. Requires appropriate DM masking. 9. A Write command may be applied after the completion of data output. 10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or t RP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).
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256Mb DDR333/300 SDRAM
Absolute Maximum Ratings
Symbol VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT Parameter Voltage on I/O pins relative to VSS Voltage on Inputs relative to V SS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating Temperature (Ambient) Storage Temperature (Plastic) Power Dissipation Short Circuit Output Current Rating Units V V V V
-0.5 to VDDQ+ 0.5 -0.5 to +3.6 -0.5 to +3.6 -0.5 to +3.6
0 to +70
C C
W mA
-55 to +150
1.0 50
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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Capacitance
Parameter Input Capacitance: CK, CK Delta Input Capacitance: CK, CK Input Capacitance: All other input-only pins (except DM) Delta Input Capacitance: All other input-only pins (except DM) Input/Output Capacitance: DQ, DQS, DM Delta Input/Output Capacitance: DQ, DQS, DM Symbol CI1 delta CI1 CI2 delta CI2 CIO delta CIO 4.0 2.0 Min. 2.0 Max. 3.0 0.25 3.0 0.5 5.0 0.5 Units pF pF pF pF pF pF Notes 1 1 1 1 1, 2 1
1. VDDQ = VDD = 2.5V 0.2V (minimum range to maximum range), f = 100MHz, TA = 25C, VODC = VDDQ/2 , VOPeak -Peak = 0.2V. 2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match input propagation times of DQ, DQS and DM in the system.
DC Electrical Characteristics and Operating Conditions
Symbol VDD VDDQ VSS, VSSQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIRatio II IOZ IOH IOL Supply Voltage I/O Supply Voltage Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (System) Input High (Logic1) Voltage Input Low (Logic0) Voltage Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs V-I Matching Pullup Current to Pulldown Current Ratio Input Leakage Current Any input 0V VIN VDD ; (All other pins not under test = 0V) Output Leakage Current (DQs are disabled; 0V Vout VDDQ Output Current: Nominal Strength Driver High current (VOUT = VDDQ -0.373V, min VREF, min VTT ) Low current (VOUT= 0.373V, max VREF, max V TT) Parameter
(0C TA 70C; VDDQ = 2.5V 0.2V, VDD = + 2.5V 0.2V, see AC Characteristics)
Min 2.3 2.3 0 0.49 x VDDQ VREF - 0.04 VREF + 0.15 - 0.3 - 0.3 0.30 0.71 -5 -5 - 16.8 mA 16.8 1 Max 2.7 2.7 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 1.4 5 5 A A Units V V V V V V V V V 1, 2 1, 3 1 1 1 1, 4 5 1 1 Notes 1 1
1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on V REF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in tHalf-he DC level of V REF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK. 5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tempera-ture and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
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256Mb DDR333/300 SDRAM DC Electrical Characteristics and Operating Conditions
Symbol IOHW IOLW Parameter Output Current: Half- Strength Driver High current (VOUT = VDDQ -0.763V, min VREF, min VTT ) Low current (VOUT= 0.763V, max VREF, max V TT)
(0C TA 70C; VDDQ = 2.5V 0.2V, VDD = + 2.5V 0.2V, see AC Characteristics)
Min - 9.0 mA 9.0 1 Max Units Notes
1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on V REF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in tHalf-he DC level of V REF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK. 5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tempera-ture and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
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256Mb DDR333/300 SDRAM AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, I DD Specifications and Conditions, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, I DD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and I DD tests may use a V IL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between V IL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input low (high) level.
AC Output Load Circuit Diagrams
VTT
50 Output (VOUT) Timing Reference Point
30pF
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256Mb DDR333/300 SDRAM DQS/DQ/DM Slew Rate
Parameterl Symbol Min DCS/DQ/DM input slew rate 1. Measured between V IH (DC), V
IL (DC),
DDR333 (-6) Max TBD
Unit
Notes
DCSLEW and V
IL (DC),
TBD V
IH (DC).
V/ns
1,2
2. DQS, DQ, and DM input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal tran-sition through the DC region must be monotonic..
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AC Input Operating Conditions (0 C TA 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC
Characteristics)
Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 1. 2. 3. 4. Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS, and DM Signals Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals Input Differential Voltage, CK and CK Inputs Input Crossing Point Voltage, CK and CK Inputs 0.62 0.5*V DDQ - 0.2 Min VREF + 0.31 VREF - 0.31 VDDQ + 0.6 0.5*VDDQ + 0.2 Max Unit V V V V Notes 1, 2 1, 2 1, 2, 3 1, 2, 4
Input slew rate = 1V/ns. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Characteristics)
Symbol
IDD Specifications and Conditions (0 C TA 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC
Parameter/Condition Operating Current: one bank; active / precharge; tRC = tRC (min); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; active / read / precharge; Burst = 2; tRC = tRC (min); CL = 2.5; IOUT = 0mA; address and control inputs changing once per clock cycle Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (max) Idle Standby Current: CS VIH (min); all banks idle; CKE VIH (min); address and control inputs changing once per clock cycle Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (max) Active Standby Current: one bank; active / precharge; CS VIH (min); CKE VIH (min); tRC = tRAS (max); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; IOUT = 0mA Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL = 2.5 Auto-Refresh Current: tRC = t RFC (min) Self-Refresh Current: CKE 0.2V Operating current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; t RC = t RC (min); I OUT = 0mA. DDR333 tCK=6ns 85 DDR333 tCK=6.6ns Unit Notes
IDD0
mA
1
IDD1
110
mA
1
IDD2P IDD2N IDD3P
15 35 15
mA mA mA
1 1 1
IDD3N
60
mA
1
IDD4R
165
mA
1
IDD4W IDD5 IDD6 IDD7
150 170 3 150
mA mA mA mA
1 1 1, 2 1
1. IDD specifications are tested after the device is properly initialized. 2. Enables on-chip refresh and address counters.
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256Mb DDR333/300 SDRAM
Electrical Characteristics & AC Timing - Absolute Specifications
DDR333 (-6) Min tAC tDQSCK tCH tCL tCK tDH tDS tDIPW tHZ tLZ tDQSQ tHP tQH tDQSS tDQSL,H tDSS tDSH tMRD tWPRES tWPST tWPRE tIH tIS tIH tIS tIPW tRPRE tRPST tRAS DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CL = 2.5 Clock cycle time CL = 2.0 DQ and DM input hold time DQ and DM input setup time DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK Data-out low-impedance time from CK/CK DQS-DQ skew (DQS & associated DQ signals) minimum half clk period for any given cycle; defined by clk high (tCH ) or clk low (t CL) time Data output hold time from DQS Write command to 1st DQS latching transition DQS input low (high) pulse width (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Input pulse width Read preamble Read postamble Active to Precharge command min (tCH, tCL) tHP - tQHS 0.75 0.35 0.2 0.2 2 x tCK 0 0.40 0.25 0.75 0.75 0.8 0.8 2.2 0.9 0.40 42 1.1 0.60 120,000 0.60 1.25 7.5 0.45 0.45 1.75 - 0.7 - 0.7 + 0.7 + 0.7 + 0.4 12 7.5 0.5 0.5 - 0.7 - 0.7 0.45 0.45 6 Max + 0.7 + 0.7 0.55 0.55 12 Min
(0 C TA 70 C; VDDQ = 2.5V 0.2V; V DD = 2.5V 0.2V, See AC Characteristics) (Part 1 of 2)
DDR300 (-66) Max + 0.75 + 0.75 0.55 0.55 12 ns 12 ns ns ns + 0.57 + 0.75 + 0.5 min (tCH, tCL) tHP - tQHS 0.75 0.35 0.2 0.2 2 x tCK 0 0.40 0.25 0.9 0.9 1.0 1.0 2.2 0.9 0.40 45 1.1 0.60 120,000 0.60 1.25 ns ns ns tCK tCK tCK tCK tCK tCK ns ns tCK tCK ns ns ns ns ns tCK tCK ns 1-4, 15,16 1-4, 15,16 1-4 1-4, 5 1-4, 5 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4, 7 1-4, 6 1-4 2-4, 9,11,12 2-4, 9,11,12 2-4, 10, 11,12,14 2-4, 10, 11,12,14 2-4, 12 1-4 1-4 1-4 1-4 ns ns tCK tCK 1-4 1-4 1-4 1-4
Symbol
Parameter
Unit
Notes
- 0.75 - 0.75 0.45 0.45 6.6
1.75 - 0.75 - 0.75
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256Mb DDR333/300 SDRAM Electrical Characteristics & AC Timing - Absolute Specifications
DDR333 (-6) Min tRC tRFC tRCD tRAP tRP tRRD tWR tDAL tWTR tXSNR tXSRD tREFI Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Active to Read Command with Autoprecharge Precharge command period Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval 60 72 18 18 18 12 15 (tWR /tCK) + (tRP/tCK) 1 75 200 7.8 Max Min 65 75 20 20 20 15 15 (tWR/tCK) + (tRP/tCK) 1 75 200 7.8
(0 C TA 70 C; VDDQ = 2.5V 0.2V; V DD = 2.5V 0.2V, See AC Characteristics) (Part 2 of 2)
DDR300 (-66) Max ns ns ns ns ns ns ns tCK tCK ns tCK s 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4,13 1-4 1-4 1-4 1-4, 8
Symbol
Parameter
Unit
Notes
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256Mb DDR333/300 SDRAM Electrical Characteristics & AC Timing - Absolute Specifications Notes
1. Input slew rate = 1V/ns. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT . 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on t DQSS . 8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9. For command/address input slew rate 1.0V/ns. Slew rate is measured between V OH (AC) and V OL (AC). 10. For command/address input slew rate 0.5V/ns and < 1.0V/ns. Slew rate is measured between VOH (AC) and V OL (AC). 11. CK/CK slew rates are 1.0V/ns. 12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
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14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns.
Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns delta ( t IS) 0 +50 +100
IH (AC) to
delta ( t IH) 0 0 0 V
IL (AC) or
Unit ps ps ps
Notes 1,2 1,2 1,2
1. Input slew rate is based on the lesser of the slew rates determined by either V transitions.
V IH (DC) to V IL (DC) , similarly for rising
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on eachdevice.
15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns.
Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns delta ( t DS) 0 +75 +150 delta ( t DH) 0 +75 +150
IL (AC) or
Unit ps ps ps V IH (DC) to V
IL (DC) ,
Notes 1,2 1,2 1,2
1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V transitions.
similarly for rising
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on eachdevice.
16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH) in the case where DQ, DM, and DQS slew rates differ.
Input Slew Rate 0.0 V/ns 0.25 V/ns 0.5 V/ns delta ( t DS) 0 +50 +100 delta ( t DH) 0 +50 +100
IH (AC) to
Unit ps ps ps
Notes 1,2,3,4 1,2,3,4 1,2,3,4
1. Input slew rate is based on the lesser of the slew rates determined by either V transitions.
V
IL (AC) or
V IH (DC) to V IL (DC) , similarly for rising
2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. 3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in t
DS and
t
DH of
100 ps.
4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
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Package Dimensions (400mil; 66 lead; Thin Small Outline Package)
Detail A
22.22 0.10
10.16 . 0.13 Lead #1
11.76 0.20 Seating Plane 0.10 0.25 Basic Gage Plane
0.65 Basic
0.30
+ 0.03 - 0.08
0.71REF
Detail A
1.20 Max
0.5 0.1 0.05 Min
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM Package Dimensions (
60 balls ; 0.8mmx1.0mm Pitch ; CSP Package)
8.5 1.05 0.80
0.50 Dia. 0.45 2.25 15.50
1.00
0.80
0.35 1.15
Note : All dimensions are typical unless otherwise stated. Unit : Millimeters
Preliminary
10/01
27
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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